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HCTS160T
Data Sheet July 1999 File Number
4626.1
Radiation Hardened Synchronous Counter
Intersil's Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HCTS160T is a Radiation Hardened High Speed Presettable BCD Decade Synchronous Counter that features an asynchronous reset and look-ahead carry logic. Counting and parallel presetting are accomplished synchronously with the low-to-high transition of the clock. A low level on the synchronous parallel enable input, SPE, disables counting and allows data at the preset inputs, P0 P3, to be loaded into the counter. The counter is reset by a low on the master reset input, MR. Two count enables, PE and TE are provided for n-bit cascading. TE also controls the terminal count output, TC. The terminal count output indicates a maximum count for one clock pulse and is used to enable the next cascaded stage to count.
Features
* QML Class T, Per MIL-PRF-38535 * Radiation Performance - Gamma Dose () 1 x 105 RAD(Si) - Latch-Up Free Under Any Conditions - SEP Effective LET No Upsets: >100 MEV-cm2/mg - Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) * 3 Micron Radiation Hardened SOS CMOS * Fanout (Over Temperature Range) - Standard Outputs 10 LSTTL Loads * Significant Power Reduction Compared to LSTTL ICs * DC Operating Voltage Range: 4.5V to 5.5V * LSTTL Input Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min * Input Current Levels Ii 5mA at VOL, VOH
Pinouts
HCTS160DTR (SBDIP), CDIP2-T16 TOP VIEW
MR 1 CP 2 16 VCC 15 TC 14 Q0 13 Q1 12 Q2 11 Q3 10 TE 9 SPE
Specifications
Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the HCTS160T are contained in SMD 5962-95742. A "hot-link" is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp Intersil`s Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp
P0 3 P1 4 P2 5 P3 6 PE 7 GND 8
Ordering Information
ORDERING NUMBER 5962R9574201TEC 5962R9574201TXC PART NUMBER HCTS160DTR HCTS160KTR TEMP. RANGE (oC) -55 to 125 -55 to 125
MR CP P0 P1 P2
HCTS160KTR (FLATPACK), CDFP4-F16 TOP VIEW
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 TE SPE
NOTE: Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
P3 PE GND
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 Satellite Applications FlowTM (SAF) is a trademark of Intersil Corporation.
HCTS160T Functional Diagram
P0 3 P1 4 P2 5 P3 6
SPE MR Q3 Q0 Q3 Q0 CP MR D0 T0 Q0 CP Q0 P MR D1 T1 CP Q1 P MR D2 T2 CP Q2 P MR D3 T3 Q3 CP Q0 P Q3 Q3 Q2 Q3 Q0 Q1
Q1 Q0 Q2 Q0 Q3
PE TE
GND 8
VCC 16 Q0 14 TC 15 Q1 13 Q0 12 Q1 11
TRUTH TABLE INPUTS OPERATING MODE Reset (Clear) Parallel Load MR L H H Count Inhibit H H H X X CP X PE X X X h l (Note 2) X TE X X X h X l (Note 2) SPE X l l h (Note 3) h (Note 3) h (Note 3) Pn X l h X X X Qn L L H Count qn qn OUTPUTS TC L L (Note 1) (Note 1) (Note 1) L
H = HIGH voltage level. L = LOW voltage level. h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition. l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition. X = Immaterial. q = Lower case letter indicate the state of the referenced output prior to the LOW-to-HIGH clock transition. = LOW-to-HIGH clock transition. NOTES: 1. The TC output is HIGH when TE is HIGH and the counter is at terminal count (HHHH for 161 and HLLH for 160). 2. The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation. 3. The LOW-to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation.
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HCTS160T Die Characteristics
DIE DIMENSIONS: (2642m x 2184m x 533m 51.0m) 104 x 86 x 21mils 2mil METALLIZATION: Type: Al Si Thickness: 11.0kA 1kA SUBSTRATE POTENTIAL: Unbiased Silicon on Sapphire BACKSIDE FINISH: Sapphire PASSIVATION: Type: Silox (SiO2) Thickness: 13.0kA 2.6kA WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: 676 PROCESS: CMOS SOS
Metallization Mask Layout
HCTS160T
CD (2) MR (1) VCC (16)
(15) TC P0 (3)
(14) Q0 P1 (4)
(13) Q1
P2 (5)
(12) Q2 P3 (6)
(11) Q3 PE (7)
(8) GND
(9) SPE
(10) TE
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCTS160 is TA14445A.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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